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Piezoelectric Ring Chips and Stacks, 2.6 µm to 9.5 µm Travel
8.3 mm OD, 3.0 mm ID
Silver Dot Indicates Positive Electrode, 75 mm Wires
Top View of the PA44LE
Flat Ceramic Endplates on Both Ends, 75 mm Wires
3 mm Inner Diameter (ID)
8.3 mm Outer Diameter (OD)
6.0 mm OD, 2.5 mm ID
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A silver dot indicates the positive electrode (above, left). There is no mark next to the negative electrode (above, right).
Thorlabs offers piezoelectric ring actuators as a chip with bare electrodes, chip with pre-attached wires, and as a discrete stack consisting of multiple chips bonded via epoxy and glass beads. Ring chips with 8.3 mm OD and 3.0 mm ID provide a maximum free stroke of 2.6 µm; discrete stacks with this cross-section provide up to 9.0 µm of travel. Ring chips with 6.0 mm OD and 2.5 mm ID provide a maximum free stroke of 2.7 µm; discrete stacks with this cross-section provide up to 9.5 µm of travel.
The central through hole makes these products ideal for laser tuning and micro-dispensing applications. They have a drive voltage range of 0 - 150 V; for a complete list of specifications, see the tables below. The flat endfaces of the PK44LA2P2 and PK44RB52 stacks are fitted with ceramic end plates.
Circular vs. Square Outer Dimensions
Piezo Chip Construction and Operation
The maximum displacement of these actuators is achieved when they are preloaded with the maximum displacement load, which is specified for each product. The actual value of the maximum displacement varies for each item and must be experimentally determined; however, the maximum displacement will always be larger than the free stroke displacement. Please note that when mounting a load onto the piezoelectric chip, the force should be directed along the actuator's axis of displacement. For more details see the Operation tab.
Piezo chips with custom dimensions, voltage ranges, and coatings are available. Additionally, customers can order these piezo chips in high-volume quantities. Please contact Tech Support for more information.
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Dicing the PZT Block into Individual Elements
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Chips After Binder Burnout and Sintering
Thorlabs' In-House Piezoelectric Manufacturing
Our piezoelectric chips are fabricated in our production facility in China, giving us full control over each step of the manufacturing process. This allows us to economically produce high-quality products, including custom and OEM devices. A glimpse into the fabrication of our piezoelectric chips follows. For more information about our manufacturing process and capabilities, please see our Piezoelectric Capabilities page.
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Figure 1: Schematic of TA0505D024W Piezo Chip Showing the + Mark Close to the Positive Electrode
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Figure 2: Schematic of PK4DMP2 Piezo Stack Showing the Line of + Marks Close to the Positive Electrode
Soldering Wire Leads to the Electrodes
Interfacing a Piezoelectric Stack with a Load
Operating Under High-Frequency Dynamic Conditions
Estimating the Resonant Frequency for a Given Applied Load
Quick changes in the applied voltage result in fast dimensional changes to the piezoelectric stack. The magnitude of the applied voltage determines the nominal extension of the stack. Assuming the driving voltage signal resembles a step function, the minimum time, Tmin, required for the length of the actuator to transition between its initial and final values is approximately 1/3 the period of resonant frequency. If there is no load applied to the piezoelectric stack, its resonant frequency is ƒo and its minimum response time is:
After reaching this nominal extension, there will follow a damped oscillation in the length of the actuator around this position. Controls can be implemented to mitigate this oscillation, but doing so may slow the response of the actuator.
Applying a load to the actuator will reduce the resonant frequency of the piezoelectric stack. Given the unloaded resonant frequency of the actuator, the mass of the stack, m, and the mass of the load, M, the loaded resonant frequency (ƒo') may be estimated:
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Figure 3: Diagram of Piezo Stack Insulation Methods:
(a) In-Chip Insulation Used in Standard Chips and Discrete Stacks,
(b) On-Stack Insulation Used in Co-Fired Stacks
Co-Fired Piezo Chips, Co-Fired Piezo Stacks, and Discrete Piezo Stacks
In the case of the chips (In-Chip Insulation), the internal electrodes of opposite polarities alternate. Each internal electrode layer is shorter than the full width of the piezo layer. All electrodes of one polarity have edges that are flush with one side of the chip, and all electrodes with the opposite polarity are flush with the opposite side of the chip. Because the electrode does not extend all the way to the opposite edge, the far end of the electrode is completely surrounded by PZT material. The PZT material enclosing the end of the electrode is insulating, which electrically isolates this electrode from the supply electrode of opposite polarity. This approach to electrically insulating the electrodes creates a region of stress at the edge of the electrode. The stress arises both due the abrupt change in thickness on either side of the electrode edge, as well as the tensile stress created when the PZT material sandwiched between electrodes responds to an applied voltage drive signal, but the insulating PZT material beyond the edge of the electrodes does not. This stress limits the maximum height of chips manufactured using this approach. The height of chips are limited to ensure internal stresses are low and do not affect lifetime or performance. Chips are sealed in a ceramic layer that offers superior resistance to humidity and heat than epoxy resin coatings.
One way of increasing the height, and therefore the maximum stroke, of piezo actuators based on these chips is to fabricate discrete piezo stacks. These are manufactured by bonding multiple chips together in series using a glass-bead epoxy. Discrete stacks can be fabricated to substantially longer lengths than co-fired chips or stacks, and this allows them to achieve higher maximum displacements while maintaining sub-millisecond response times and a low drive voltage range. As the constituent chips are sealed within a ceramic barrier layer, discrete stacks have superior resistance to humidity and heat than co-fired stacks, which are sealed in an epoxy resin coating.
In the case of co-fired stacks (On-Stack Insulation), the electrodes extend across the full width of the PZT layers. The edges of the electrodes are flush with all four sides of the stack, including the side with the supply electrode of opposite polarity. The edge of the internal electrode is insulated from that supply electrode by a layer of glass filament applied to the side of the stack. Precision localized application of the glass filament ensures that the electrode edge is electrically isolated from the supply electrode, and that the filament is applied over minimal surface area; the ability of the supply electrode to make electrical connections to the desired internal electrodes is not affected, and the small amount of applied glass filament does not affect the operation of the actuator. With their full-width electrodes, piezo actuators made using this insulating approach are characterized by homogeneous internal stress. Co-fired stacks can therefore be fabricated with greater heights than chips fabricated using the in-chip insulation approach. Co-fired stacks also have a higher percentage of active PZT material than the discrete stacks, which include inactive bonding layers of glass-bead epoxy. They are coated in an epoxy resin.
Estimating Device Lifetime for DC Drive Voltage Conditions
A ceramic moisture-barrier layer that insulates Thorlabs' piezoelectric devices on four sides is effective in minimizing the effects of humidity on device lifetime. As there is interest in estimating the lifetime of piezoelectric devices, Thorlabs conducted environmental testing on our ceramic-insulated, low-voltage, piezoelectric actuators. The resulting data were used to create a simple model that estimates the mean time to failure (MTTF), in hours, when the operating conditions of humidity, temperature, and applied voltage are known. The estimated MTTF is calculated by multiplying together three factors that correspond, respectively, to the operational temperature, relative humidity, and fractional voltage of the device. The fractional voltage is calculated by dividing the operational voltage by the maximum specified drive voltage for the device. The factors for each parameter can be read from the following plots, or they may be calculated by downloading the plotted data values and interpolating as appropriate.
In the following trio of plots, the solid-line segment of each curve represents the range of conditions over which Thorlabs performed testing. These are the conditions observed to be of most relevance to our customers. The dotted-line extensions to the solid-line segments represent extrapolated data and represent a wider range of conditions that may be encountered while operating the devices.
Calculation of MTTF to Estimate Lifetimes: MTTF = fV * fT * fH
Given the relative humidity conditions, device temperature, and DC operational voltage, the device lifetime can be estimated. It is the product of voltage, temperature, and humidity factors, which can be determined using relationships plotted at right, lower-right, and below.
As an example, when a device of type PK2FSF1 is operated with a voltage of 60 V, at a temperature of 30 °C, and in an environment with 75% relative humidity:
Then MTTF = 472 * 83 * 2.8 = 99234.8 hours, which is greater than 11 years.
Note that relationships graphed on this page apply only to Thorlabs' ceramic-insulated, low-voltage, piezoelectric stack actuators.
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For an Excel file containing these fH vs. relative humidity data, please click here.
The data used to generate these temperature, voltage, and humidity factor plots resulted from the analysis of measurements obtained from testing devices under six different operational conditions. Different dedicated sets of ten devices were tested under each condition, with each condition representing a different combination of operational voltage, device temperature, and relative humidity. After devices exhibit leakage current levels above a threshold of 100 nA, they are registered as having failed. The individual contributions of temperature, humidity, and voltage to the lifetime are determined by assuming:
where A1, A2, A3, b1, b2, and c are constants determined through analysis of the measurement data, V is the DC operational voltage, T is the device temperature, and H is the relative humidity. Because the MTTF has a different mathematical relationship with each factor, the dependence of the MTTF on each factor alone may be determined. These are the data plotted above. The regions of the above curves marked by the blue shading are derived from experimental data. The dotted regions of the curves are extrapolated.
Lifetime testing of these devices continues, and additional data will be published here as they become available.